发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the offset of a comparator by arranging a 1st protecting element for gate oxide film protection for a metal wire connected to a 1st MOS transistor(TR), forming a differential stage and a 2nd protecting element for gate oxide film protection for a metal wire connected to a 2nd MOS TR. SOLUTION: A 1st protecting element for gate oxide film protection is arranged for the metal wire connected to the gate electrode of the 1st MOS TR forming the differential stage. Furthermore, a 2nd protecting element for gate oxide film protection is arranged for the metal wire connected to the gate electrode of the 2nd MOS TR forming the differential stage. For example, a PMOS differential comparator circuit has a normally off type NMOS TR Q5 formed at the gate electrode of a 1st PMOS TR Q1 forming a differential stage. Furthermore, a normally off type NMOS TR Q6 is formed at the gate electrode of a 2nd PMOS TR Q2.
申请公布号 JP2000236237(A) 申请公布日期 2000.08.29
申请号 JP19990034822 申请日期 1999.02.12
申请人 SEIKO INSTRUMENTS INC 发明人 INOUE SHIGETO
分类号 H03K5/08;(IPC1-7):H03K5/08 主分类号 H03K5/08
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