| 摘要 |
An arrangement in a processor circuit for concurrently executing a plurality of instructions. An instruction control unit concurrently supplies a plurality of instruction addresses to an instruction memory. Each clock cycle, the instruction memory receives one instruction address from the instruction control unit based on a count value and selectively fetches and outputs corresponding to the received instruction address. An instruction decoder decodes, each clock cycle, the instruction output from the instruction memory the preceding clock cycle while identifying a memory address and an instruction operation for each fetched instruction. A memory interface, based on the count value, selectively supplies to an external memory, each clock cycle, one of the supplied memory addresses and identified by the instruction decoder for the respective fetched instructions. A logic unit, based on the count value also, selectively executes, each clock cycle, the instruction operation for the corresponding fetched instruction using memory data retrieved from the supplied memory address. The instruction control unit has program counter circuits that respectively output the instruction addresses. An instruction controller generates program instruction control signals for each of the program counter circuits in response to a corresponding instruction sequence.
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