| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and a clock delay adjusting method for automatically adjusting the supply of a clock signal to an SDRAM at optimum timing. SOLUTION: Clock passes having respectively different delay amounts are formed by delaying a system clock SC by a buffer row BR and connecting some buffer outputs to a selector SE1. When a test instruction signal is inputted to a test mode terminal TT, an output from a selector SE2 is set up as the pass number of a pass number register group REP1, its clock pass is selected by the selector SE1 and a memory clock MC is supplied to an SDRAM 2. The same pass number data are written in the SDRAM 2 and then read out from the SDRAM 2 and whether the written data coincide with the read data or not is judged. The judgment is repeated by an incrementor INC by successively increasing pass numbers, the mean value of pass numbers judged as coincident pass numbers is stored in a pass number register group REP2 and the clock pass is used as an optimum clock pass.</p> |
