| 摘要 |
PROBLEM TO BE SOLVED: To enable space saving, easy manufacture, and reduction of clock skew, even if temperature, power voltage and process variations are fluctuated. SOLUTION: Delay circuit trees 112 and 113 are formed by interconnecting a plurality of buffers in a power trunk 114, and a clock signal is supplied to macrocells 104 and 105 via the delay circuit trees 112 and 113. Thereby an excess area for delay circuits can be eliminated and a clock signal line causing a delay does not span trees, thus facilitating delay calculation and layout verification.
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