发明名称
摘要 This texture pattern memory circuit is composed of a multi-texture pattern memory 2A, a writing device 3A and a texel selector 4A. The multi-texture pattern memory 2A includes an adder 5A, a subtracter 6A, selectors 7A and 8A, 1st to 4th address converting devices 9A1 through 9A4, and 1st to 4th memory modules 10A1 through 10A4. The texel selector 4 selects only the necessary data from the texel data outputted from the multi-texture pattern memory 2A. <IMAGE>
申请公布号 JP3081774(B2) 申请公布日期 2000.08.28
申请号 JP19950125384 申请日期 1995.05.24
申请人 发明人
分类号 G09G5/39;G06F12/00;G06F12/06;G06T1/60;G06T11/20;G06T15/00;(IPC1-7):G06T15/00;G06T11/00 主分类号 G09G5/39
代理机构 代理人
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