| 摘要 |
PURPOSE: A data cache memory with data storage and tag logic with different clocks is provided for use as an L0 data cache in a microprocessor having plural execution core section operation at a different clock frequencies. CONSTITUTION: A processor(210) includes a cache memory with a data storage unit(310) operating at a first clock frequency, and a tag unit and hit/miss logic operating at a second clock frequency different than the first clock frequency. The data storage unit is advantageously clocked faster than the tag unit and hit/miss logic, such as 2 times faster. The cache structure is used as an L0 data cache in a microprocessor, especially in one which has plural execution core sections operating at the different clock frequencies. The processor can utilize speculative data and has a replay function when the speculative data read from the cache turns out to be invalid.
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