FIRM WORDLINE ACTIVATION DELAY MONITORING CIRCUIT USING PLURALITY OF SAMPLE WORDLINES

摘要

PURPOSE: A firm wordline activation delay monitoring circuit using a plurality of sample wordlines is provided to reflect actual delay more previously in case that a wordline in a semiconductor memory is activated and to achieve a sample wordline delay monitoring circuit using a decoding circuit intimately complied with a decoding circuit of a specific selection wordline. CONSTITUTION: A multiple bank memory(10), such as a DRAM, comprises a couple of memory units(12) provided with column decoder/sense amplifiers(19). Each memory unit(12) is determined as a memory domain comprising a memory array accessed by a set of row decoder/row control circuit in a rib(14) of the multiple bank memory(10). A first memory unit(12) comprises 4 banks(16a-16d) and a second memory unit(12) and 4 banks(16e-16h). Each bank has a plurality of sub arrays(18) and is determined as a memory domain which provides access to a plurality of data words. Each sub array(18) is determined as a bank array domain divided from other sub array by a first column decoder/sense amplifier.