发明名称 SEMICONDUCTOR DEVICE MAKING EASILY CYCLE TIME HIGHLY SPEEDY UNDER CHIP SIZE LIMIT CONDITION OF IMPLEMENTING MPU AND DRAM IN SAME CHIP
摘要 PURPOSE: A semiconductor device easily adjusting the cycle time is provided to shorten the cycle time by alleviating a load of address signals after an address register that a clock signal is input as a latch signal. CONSTITUTION: A semiconductor device comprises an MPU(micro processing unit), a DRAM(dynamic random access memory), a plurality of address registers, and a plurality of address delay compensators. The MPU, installed in a chip, generates clock signals and address signals. The DRAM, also installed in the same chip, input the clock signals and the address signals. The address registers latches the address signals in response to the clock signals. The address delay compensators, installed at a front end of the address registers, compensates the address signal transmission delay to make the delay time, expressing the passage time from the generation of the address signal at the MPU to the entrance of the address signal into the registers, limited within a set range.
申请公布号 KR20000052418(A) 申请公布日期 2000.08.25
申请号 KR19990055089 申请日期 1999.12.06
申请人 NEC CORPORATION 发明人 SGIVAYASI DADAHICO
分类号 G06F13/14;G06F1/10;G06F12/00;G06F12/02;G06F12/08;G06F15/78;G11C11/401;G11C11/408;H01L21/822;H01L27/04;H01L27/10;(IPC1-7):G06F13/14 主分类号 G06F13/14
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