| 摘要 |
PURPOSE: A synchronous semiconductor memory device is provided to optimize a design by minimizing an operation margin by setting a process characteristic, a power characteristic and a temperature characteristic substantially the same over a measured value of a time between an activation and a sense completion. CONSTITUTION: A first signal generator (13) generates a first control signal consisting of pulses generated by being synchronized with a cycle of a clock signal, after a predetermined time elapses from a timing at which the activation signal is applied to effect a row of a memory cell array assigned by a row address. A second signal generator (15) generates a pulse of a second control signal consisting of pulses generated by being synchronized with a cycle of the clock signal, after a timing that a read command or a write command is applied to access the memory cell array. A third signal generator (19) determines a timing to assign a column address of a memory cell array generated on the basis of a delayed signal among the first control signal and the second control signal, and generates a third control signal.
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