| 摘要 |
<p>A global signal distribution architecture for an FPGA architecture that has a plurality of multiplexers (80) with inputs and an output. The outputs of the plurality of multiplexers (80) are coupled to global I/O lines (16) that are coupled to a global signal distribution bus (18) spanning a highest level in the FPGA architecture. A plurality of switch matrices (106) are coupled to global signal distribution bus (18) and to a plurality of utility conductors (108) that are coupled to at least one multiplexer associated with a lowest level in the FPGA architecture.</p> |
