| 摘要 |
A circuit (34) receives data asynchronously from a bus (48) on which the dat a is transferred on both rising and falling edges of a control signal (H- STROBE), and provides the data to an output (FIFO_DIN) synchronously with a local clock (SYSCLK). The circuit (34), which may be used in an Ultra DMA controller or other type of device (2) that receives data according to a dua l clocked transfer scheme, advantageously, allows the dual edge clocked data t o be received using the same controller clock frequency that would be used if the data were transferred only on a single edge. The circuit (34) includes a strobe generator (22) that generates strobes in response to the edges (502, 504, 506) of the control signal. The data from the bus (48) is provided to t wo temporary storage units (24, 26), one which stores the data transferred on rising edges and one which stores the data transferred on falling edges. The data is provided synchronously to the output of the circuit by using the strobes generated by the strobe generator (22) to select between the two temporary storage units (24, 26).
|
