Multi port semiconductor memory device, e.g. dual port SRAM, has a memory cell array, input and output circuits operating in single clock cycle

摘要

The input circuit (16) reacts to a write control signal (102) to store a write datum in a memory cell of the write address during a clock cycle of a system signal (108). The output circuit (18) reacts to a read-out control signal (106) for a datum read-out from an addressed cell during the same clock cycle. A coincidence detector section (17) generates a coincidence signal (107) on read-out and write address coincidence. A bridging (19) and a time control circuits (22) complete the memory. The read-out control signal precedes the write control signal, if there is no coincidence signal, but with the coincidence signal present the read-out and write signals are generated at the same time. Independent claims are included for the control method.