发明名称 Integration of bipolar and CMOS devices for sub-0.1 micrometer transistors
摘要 <p>Form a semiconductor device with dielectric, isolation structures in a top surface of a silicon semiconductor substrate, separating the substrate into emitter, NMOS and PMOS areas. Form a gate oxide layer above the isolation structures on the top surface of the silicon semiconductor substrate. Form a conductive polysilicon layer above the thin silicon oxide layer. Mask the NMOS and PMOS regions of the substrate with an emitter mask having a window over the emitter area of the substrate. Ion implant emitter dopant into a portion of the conductive polysilicon layer over the emitter area of the substrate through the window in the emitter mask. Strip the emitter mask. Anneal the substrate including the thin silicon oxide layer, and the polysilicon layer to drive the dopant into an emitter region in the emitter area in the substrate. Form doped source/drain regions and a base in the emitter area of the substrate. &lt;IMAGE&gt;</p>
申请公布号 EP1030363(A2) 申请公布日期 2000.08.23
申请号 EP19990480058 申请日期 1999.07.09
申请人 CHARTERED SEMICONDUCTOR MANUFACTURING PTE LTD. 发明人 PAN, YANG;LIU, ERZHUANG
分类号 H01L21/8249;H01L27/06;(IPC1-7):H01L21/824 主分类号 H01L21/8249
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