发明名称 Method of forming trench capacitor DRAM cell
摘要 A method of forming a dynamic random access memory cell in a semiconductor substrate. The cell has a transistor in an active area of the semiconductor substrate electrically coupled to a storage capacitor through a buried strap or coupling region. The method includes forming an electrode for the capacitor in a lower portion of a trench in the semiconductor substrate. A sacrificial material is formed on the sidewall portion of the trench, such sacrificial material extending from the surface of the semiconductor substrate into the substrate beneath the surface of the semiconductor substrate. The active area for the transistor is delineated and includes forming a covering material over the surface of the semiconductor substrate with a portion of the sacrificial material being projecting through the covering material to expose such portion of the sacrificial material. Subsequent to the delineation of the active area, the covering material and the exposed portion of the sacrificial material are subjected to an etch to selectively remove the sacrificial material while leaving the covering material, such removed sacrificial material exposing the first region of a semiconductor substrate disposed beneath a surface of such substrate. The selected material is provided in the exposed portion of the semiconductor. The method is used in a variety of applications including formation of the buried strap used to electrically connect the capacitor and the transistor and formation of a vertical gate channel for the transistor of the cell. <IMAGE>
申请公布号 EP1030362(A2) 申请公布日期 2000.08.23
申请号 EP20000102126 申请日期 2000.02.04
申请人 INFINEON TECHNOLOGIES NORTH AMERICA CORP. 发明人 GRUENING, ULRIKE
分类号 H01L21/302;G11C11/413;H01L21/3065;H01L21/8242;H01L27/108;(IPC1-7):H01L21/824 主分类号 H01L21/302
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