A method for reducing transition time in a PLL frequency synthesizer having a programmable frequency divider

摘要

For reducing the transition time which is required to switch a PLL circuit comprising a programmable frequency divider (5) from one frequency to another at least one or a certain sequence of additional intermediate divider steps are selected such that the final frequency is approached faster. Appropriate additional intermediate divider steps and their respective time duration are selected from a look-up table or defined according to an algorithm depending on the respectively required frequency change and in consideration of the response of the PLL upon divider switching. No additional or modified hardware is required. The invention is applicable for all kinds of systems comprising programmable PLL circuits. <IMAGE>