发明名称 |
Fractional phase-locked loop coherent frequency synthesizer |
摘要 |
Present-day single or multiple fractional phase-locked loop frequency synthesizers are not phase coherent for they use a digital accumulator modulo a number P with a variable increment K, whose state is a function of the history of the change in values that have been imposed on the increment. This lack of phase coherence rules out the use of these synthesizers in certain fields such as that of Doppler radars. A novel type of single or multiple fractional phase-locked loop frequency synthesizer that is coherent in phase is proposed herein. This type of synthesizer comprises one or more counters with an increment of one, having their rate set by the reference oscillator of the synthesizer and being used in phase memories to enable changes in the increment or increments following a change in the fractional division ratio at instants that are synchronous with the reference oscillator.
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申请公布号 |
US6107843(A) |
申请公布日期 |
2000.08.22 |
申请号 |
US19980070157 |
申请日期 |
1998.04.30 |
申请人 |
THOMSON-CSF |
发明人 |
DE GOUY, JEAN-LUC;GABET, PASCAL |
分类号 |
H03L7/183;H03L7/197;(IPC1-7):H03D3/24 |
主分类号 |
H03L7/183 |
代理机构 |
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