| 摘要 |
PROBLEM TO BE SOLVED: To enhance the efficiency of a system bus by setting a write latency variable in accordance with the CAS latency of a clock synchronization type memory. SOLUTION: In an operation at the time of setting every CAS latency CL, read latency and write latency to 2 and a burst length BL to 4, a write command Write (a), a read command Read (b) and a write command Write (c) are respectively issued at a first cycle, a second cycle and a sixth cycle as commands COM in synchronization with a clock signal CLK, In the operation of this continuous write operation-to-read operation-to-write operation, since the write latency and the read latency are both 2, an idle time is not generated on buses of input-output data I/O even at the time of the write operation-to-the read operation. Moreover, an interruption and a high impedance control in the course of a burst read are made unnecessary in the read operation-to-the write operation.
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