| 摘要 |
In a relaxed bus protocol for transferring bursts of data from a slow device to another device, a predictor generates an advance signal. The advance signal is used to load next data into an output register of the slow device, the next data can then be transferred to the other device. A validator/corrector receiving a ready signal from the second device, the validator/corrector determines that the advance signal is correctly generated by the predictor. Heuristics and a higher level protocol adjust the size and frequency of the bursts of data to achieve optimal performance, and maintain correctness of transmitted data.
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