Circuit design verification tool and method therefor using maxwell's equations

摘要

Very high speed circuits are adversely effected by parasitic capacitances and line resistances. At high speeds these values of capacitance and resistance change with frequency. A method of verification of the design of high speed circuits includes a simulation of the effects of these changes in resistance and capacitance which occur at high frequency. There is a logic component and a physical-layout component which are combined to provide a full simulation of the circuit taking into account these effects which occur at very high frequency. The physical-layout component utilizes Maxwell's equations in their entirety without removing the time dependent effects. One embodiment considers only cases defined by the bus protocol, reducing the computational penalty of complete electromagnetic simulation.