| 摘要 |
PROBLEM TO BE SOLVED: To obtain a parallel data synchronized with its own device clock and also to reduce delay time by converting the clock frequency of a serial data transmitter into a clock frequency of its own device at a serial data transmission rate. SOLUTION: This circuit is provided with a 1st register 2 which writes and stores output data of a clock/data recovery circuit 1 in turn and reads the data in the writing order and a 2nd register 3 which writes data read from the register 2 in a clock obtained by multiplying the clock of its own device by one bit at a time and collectively reads n bits in the clock of the self-device. It is further provided with a multiplication circuit 9 which inputs the clock of the its own device, multiplies it by n times and outputs it, and a frequency dividing circuit 8 which inputs a timing signal outputted from a read control circuit 7 generates a clock to the register 3 and the clock of its own device multiplied by (n) times, and performs frequency division of the multiplied clock into 1/n and generates the clock of the register 3. |
