CMOS semiconductor device comprising graded junctions with reduced junction capacitance

摘要

A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A5 implant, followed by activation annealing.