SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PROBLEM TO BE SOLVED: To accelerate the speed of an address access by reducing the wiring delay of address signals. SOLUTION: In a latch/predecoder section 3a, which is a row system address access circuit, a row address strobe signal/RAS is latched synchronously with a clock signal CLKi by an internal RAS generating circuit 13 and a row address strobe signal/RASi is outputted. An address latch circuit 14 latches an address signal AD by ANDing the signals CLKi and RASi and transmits a complementary address signal ADD to a predecode circuit 15. The circuit 15 outputs a predecode signal PD in synchronism with the signal RASi. Thus, the number of logic circuit steps to the signal PD output is greatly reduced and the row system access is made faster.