SEMICONDUCTOR MEMORY DEVICE AND DATA BUS RESET METHOD

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of accelerating operating speed and reducing power consumption. SOLUTION: A reset circuit 11 is provided with first and second reset circuit sections 11a and 11b and a control section 11c. The section 11c operates the section 11a prior to a write operation to a memory cell and operates the section 11b before a read operation. The section 11a conducts a reset operation making a first potential of an intermediate level (Vdd/2) of a high potential side power supply Vdd as a precharge potential. The section 11b conducts a reset operation making a second potential of the power supply Vdd level as a precharge potential.