| 摘要 |
PROBLEM TO BE SOLVED: To increase speed of a dispatching processing by holding status information of a CPU in an exclusive buffer and executing comparison of degrees of priority between processes by hardware. SOLUTION: This CPU status control circuit is provided with a command analyzing part 42 to decode commands to be transmitted by each of the CPUs 1 to 3 and to output analyzing results, plural status buffers 43 to 45 to hold pieces of the status information of each CPU for each CPU, a NEXT process priority degree buffer 46 to hold a degree of priority of the next process transmitted from an optional CPU together with the command, a priority degree comparing part 47 to compare degrees of priority of each process held by plural status buffers and the NEXT process priority degree buffer and to output comparison results and a control part 41 to control plural status buffers and the NEXT process priority degree buffer according to a decoding signal to be outputted by the command analyzing part and to inform the comparison results to be outputted by the priority degree comparing part to the CPU concerned.
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