发明名称 Redundant clock signal generating circuitry
摘要 A clock distribution system in a reliable electronic system includes a predetermined number of clock signal load circuits, each having a clock signal input terminal. A first clock signal generator has the same predetermined number of clock signal output terminals coupled to the clock signal input terminals of the clock signal load circuits. A second clock signal generator also has the same predetermined number of clock signal output terminals which are also coupled to the clock signal input terminals of the clock signal load circuits.
申请公布号 US6107855(A) 申请公布日期 2000.08.22
申请号 US19980156747 申请日期 1998.09.17
申请人 EMC CORPORATION 发明人 WILCOX, JEFFREY
分类号 G01R31/30;G06F1/04;G06F1/08;(IPC1-7):G06F1/04 主分类号 G01R31/30
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