Techniques for improving memory access in a virtual memory system

摘要

According to the present invention, methods and apparatus for reducing memory access latency are disclosed. When a new entry is made to translation look aside buffer, the new TLB entry points to a corresponding TLB page of memory. Concurrently with the updating of the TLB, the TLB page is moved temporally closer to a processor by storing the TLB page in a TLB page cache. The TLB page cache is temporally closer to the processor than is a main memory.