| 摘要 |
<p>An ATM cell synchronization circuit can be realized by a circuit construction operable at low speed. Cell strings developed into eight parallel strings by a serial to parallel development circuit are further developed into 8n parallel strings. A frequency of a clock signal synchronous with bytes of the input cell string is divided into n by a frequency divider circuit for lowering speed to be 1/n. The parallel developed signals are rearranged by a shifted register into a signal string for detection by HEC (Header Error Control) detecting circuit. Then, an HEC byte is detected by the HEC detecting circuit. In order to detect the HEC bytes located at n positions, n in number of HEC detecting circuits are provided, At this time, the HEC byte after n cells becomes the same position. The interval of n cell is fifty-three. Therefore, a counter counting fifty-three is provided. Respectively predetermined values are detected by the decoders to generate detection signals. The detection signals are compared with detection signals of the HEC detecting circuits. When the detection signal of the decoder and the detection signal of the HEC detecting circuit match, the start control of the counter from free-run condition, for establishing synchronized state.</p> |
