Equidistant, synchronous clock generation method for PROFIBUS-DP subscriber

摘要

The method involves generating a clock using a digital PLL and synchronising the generated clock onto the mean value of the DP clock. Preferably, the forming of the mean value is carried out with a PI controller. Jitter is reduced when adjusting the controller parameter. A time window is provided, so that delayed DP clocks are not taken into consideration when forming the mean value. When the DP clocks are delayed or fail, the output clock of the PLL is generated with unchanged frequency.