| 摘要 |
PURPOSE: A digital filter device compensating for a clock delay error of a vestigial sideband demodulator is provided to compensate for a clock delay error due to a design for a digital filter using multi clocks, whereby the digital filter is able to perform its operation without sharp increase in gate number regardless of relatively larger clock skew. CONSTITUTION: A digital filter device compensating for a clock delay error of a vestigial sideband demodulator comprises: first and second skew delayers(71,72) delaying output data from a plurality of adders by a half cycle of a system clock; a first multiplexer(73) multiplexing outputs of two adders among the plurality of adders delayed in the first and second skew retarders(71,72) and outputting the multiplexed data according to a selected signal; a second multiplexer(74) multiplexing a vestigial sideband filter coefficient and outputting it according to a selected signal; first and second retarders(75,76) delaying outputs of the first and second multiplexers(73,74) by a cycle of each system clock; a multiplexer(77) multiplexing outputs of the first and second delayers(75,76); third retarder(78) delaying an output of the multiplexer(77) by a cycle of 2 system clock; fourth delayer(79) delaying an output of the third delayer(78) for a cycle of the 2 system clock; an adder(80) adding outputs of the third and fourth delayers(78,79); fifth delayer(81) delaying an output of the adder(80) by a cycle of the 2 system clock; third skew delayer(82) delaying data of the fifth delayer(81) by a half cycle of the system clock; and sixth delayer latching an output of the third skew delayer(82) in the system clock operation and outputting the data. |
