| 摘要 |
A digital input PWM power amplifier comprises: an oversampling and noise shaping circuit receiving pulse code modulated (PCM) digital input data organized in words of a first number M of bits at a certain bit rate (Fin) and outputting pulse code modulated digital data organized in words of a smaller number N of bits at a multiple bit rate (Fin*K); a first bus transmitting a first number (P) of most significant bits (MSB) of said N bit words output from said first circuit and a second bus transmitting a second number (S) of least significant bits of said N bit words output from said first circuit; first and second PCM/PWM converters, respectively fed with said first and second number of bits transmitted through said first and said second bus, each converter including a counter driven by a clock signal (Fclock) of frequency equal to the product of the bit rate (Fin*K) of the MSB and LSB bits transmitted on the respective bus and the square of the respective number of bits (P, S) generating reference digital words composed of said respective number of bits (P, S), defining ramps of digital values with a frequency identical to said multiple bit rate (Fin*K), and a digital comparator receiving through a first input said reference digital words and through a second input the respective first and second number of bits (MSB, LSB) and outputting a respective PWM signal (MSBdig, LSBdig); the PWM signal (MSBig) output by said first converter, being summed to the so attenuated PWM signal (LSBdig) output by said second converter on the inverting input node (-) of said output power stage. <IMAGE>
|
