| 摘要 |
PURPOSE: A microprocessor is provided to reduce a command transaction overhead between a CPU core and a main memory by preparing for cash memories according to commands so that it can enhance an efficiency of the cash memories. CONSTITUTION: A microprocessor comprises a command fetcher(40) including multiplexors(12,14,16) and a signal generator(18), cash memories(20,22,24), a 4th multiplexor(26), a decoding & mapping part(28), a decoder(30) and a data interface(32). The data interface(32) has functions of interfacing addresses and data accessed by a main memory and additional cash memories, and control signals accessed via a system control bus. The decoder(30) decodes the data output from a data interface(32), and transmits the decoded data to the cash memories(20,22,24). The command fetcher(40) selectively outputs one among addresses for external commands, one among addresses for normal commands and one among addresses for subroutine commands, as addresses(VA1,VA2,VA3), and transmits a selection signal(S) to the 4th multiplexor(26) in response to a control signal(C).
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