DELAY LOCK LOOP AND ITS METHOD

摘要

PURPOSE: A delay lock loop(20) and its method is provided to generate an advanced clock signal(ICLK2) synchronized with a reference clock signal(RCLK2). CONSTITUTION: A delay lock loop(20) and its method is composed of an input buffer(21), a variable delay-reflected circuit(24), a phase shift(23), a delay controller(25), a phase sense pump(26) and a phase inversion controller(27). The variable delay-reflected circuit(24) includes multiple delay terminals. The number of enabled delay terminals is controlled by a counting signal group(QCF). The phase shift(23) ultimately compares the phase of an output signal from the variable delay-reflected circuit(24) that generates an advanced clock signal(ICLK2) and the phase of a reference clock signal(RCLK2). If the phase differential compared is higher than /2, the phase shift(23) generates an advanced clock signal(ICLK2) by inverting the delay clock signal(DCLK2). If the phase If the phase differential compared is lower than /2, the delay clock signal(DCLK2) is not inverted and generated as an advanced clock signal(ICLK2).