发明名称 |
High speed global row redundancy system |
摘要 |
A row repair system for replacing a defective primary memory row with a redundant memory row within an entire section of an integrated circuit memory chip. The system comprises a dedicated match circuit for each redundant row in a given section. The match circuit analyzes incoming address information to determine whether the address corresponds to a memory location in a specific defective row in any one of a number of sub-array blocks within the section. When such a critical address is detected, the match circuit activates circuitry which inhibits access to the defective row and enables access to its dedicated redundant row. |
申请公布号 |
US6104645(A) |
申请公布日期 |
2000.08.15 |
申请号 |
US19960659724 |
申请日期 |
1996.06.06 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
ONG, ADRIAN;ZAGAR, PAUL S. |
分类号 |
G11C29/00;(IPC1-7):G11C7/00 |
主分类号 |
G11C29/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|