SR LATCH, FLIP-FLOP AND METHOD FOR OPERATING SR LATCH

摘要

PROBLEM TO BE SOLVED: To provide an SR latch that is operated at a comparatively faster processor speed and to provide a flip-flop and a method for operating the SR latch. SOLUTION: The SR latch 30 has a signal generating block that receives a Q signal and an inverse of Q signal respectively from a set signal and a reset signal and has an idle state and a storage block 32 that receives the Q signal and the inverse of Q signal to maintain the Q signal and the inverse of Q signal at a voltage level outputted from 1st and 2nd logic blocks before the 1st and 2nd logic blocks are idle. The Q signal and the inverse of Q signal are substantially simultaneously changed in a complementary state. The signal generating block has the 1st logic block 34 and the 2nd logic block 36 to generate respectively the Q signal and the inverse of Q signal from the set signal and the reset signal and the 1st logic block 34 and the 2nd logic block 36 have an idle state.