发明名称 LOGIC SIMULATION SYSTEM
摘要 PROBLEM TO BE SOLVED: To efficiently simulate test data without any excess or shortage by changing a test data formation parameter automatically when a verification ratio becomes a predetermined condition. SOLUTION: A logic simulation system is provided with a verification ratio monitoring unit 105, a test data forming/selecting unit 12 or the like. The verification ratio monitoring unit 105 controls operated steps and unoperated steps according to logic simulation and grips the number of newly operated steps in every test data by a block unit for controlling it as a verification ratio. The test data forming/selecting unit 102 monitors the verification ratio received from the verification ratio monitoring unit 105 and changes a test data formation parameter when a verification ratio increment representing a difference between cumulative verification ratio until the previous time and the newest cumulative verification ratio is below a predetermined reference such as a tenth part of verification increment expected value computed by a predetermined way.
申请公布号 JP2000227464(A) 申请公布日期 2000.08.15
申请号 JP19990028090 申请日期 1999.02.05
申请人 HITACHI LTD 发明人 YOKOYA SHIGEKI;OGUMA TOSHIO;YAMAMOTO YOSHIHIKO;SATO TOMOHIRO
分类号 G01R31/28;G01R31/3183;G06F17/50;(IPC1-7):G01R31/318 主分类号 G01R31/28
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