Phase locked loop capable of synchronizing output clock signal with input signal when VCO controller has insensitive input voltage range

摘要

A phase locked loop has a voltage comparator (41) which compares a control voltage Vf supplied from a filter (15) to a voltage controlled oscillator (16) with a reference voltage VR1 supplied with a reference voltage supplying terminal (42). The reference voltage VR1 is not lower than a maximum voltage of an insensitive range of a VCO controller (17). When the control voltage Vf is lower than the reference voltage VR1, the voltage comparator 41 produces a logic high level signal. A charge pump (43) annuls a discharge signal supplied from a phase comparator (13) in response to the logic high level signal sent from the voltage comparator (41). The phase comparator (13) compares an input signal with an output clock signal supplied from the voltage controlled oscillator (16) to produce the discharge signal.