| 摘要 |
In a switchable multi bit DRAM, in addition to main bit line pair and a main sense amplifier, sub bit line pair and a sub sense amplifier are provided. Between the main bit line pair and the sub bit line pair, transistors are connected, and a transistor, a reference capacitor and a transistor are connected between the main bit line and the complementary sub bit line. By controlling these components, it becomes possible to use the memory cell as a 4-value memory or a binary memory. Therefore, storage capacity and power consumption can be switched.
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