发明名称 |
Programmable logic device |
摘要 |
An improved programmable logic device is disclosed. In one embodiment, the programmable logic device includes a plurality of I/O cells and a plurality of logic block clusters. Each logic block cluster has a set of logic blocks and a cluster routing pool, which provides programmable connections among the logic blocks and the I/O cells. A global routing pool provides programmable connections among the logic block clusters and the I/O cells. Each logic block includes a programmable logic array with a plurality of outputs. A product term sharing array in the logic block has a plurality of bus lines, each of which is coupled to at least one of the outputs of the programmable logic array. The product term sharing array also includes a plurality of output lines, each of which is coupled to a plurality of programmable interconnections that each provide a connection to one of the bus lines. Each output line of the product term sharing array is coupled to the same number of programmable interconnections. The logic block also includes a register coupled to at least one of the output lines of the product term sharing array. The register has a data input terminal and a data output terminal. First and second output multiplexers each have a first input terminal coupled to the data input terminal of the register and a second input terminal coupled to the data output terminal of the register.
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申请公布号 |
US6104207(A) |
申请公布日期 |
2000.08.15 |
申请号 |
US19980067318 |
申请日期 |
1998.04.27 |
申请人 |
LATTICE SEMICONDUCTOR CORPORATION |
发明人 |
CHAN, ALBERT;SHEN, JU;TSUI, CYRUS Y. |
分类号 |
H03K19/177;(IPC1-7):G06F7/38;H01L25/00 |
主分类号 |
H03K19/177 |
代理机构 |
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地址 |
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