Method for facilitating engineering changes in a multiple level circuit package

摘要

An anticipation of engineering changes to a multiple-level integrated circuit package, resulting in a significant decrease in the turnaround time required to make engineering changes. After the first pass of the design phase is complete and before manufacture has begun, surplus I/O at different package levels are wired into surplus connections involving all but the highest package level. These surplus connections are reserved for future use when engineering changes become necessary. Once manufacture is complete, the surplus connections can be converted into logical connections by ECing only the highest packaging level with the quickest turnaround time. The surplus connections also provide a means for implementing ongoing incremental engineering changes as they are needed.