发明名称
摘要 PURPOSE:To adjust the oscillating frequency quickly by providing a control circuit receiving the outputs of two frequency dividers, comparing the arrival time of the two signals and outputting a reset signal to the two frequency dividers at the arrival of the signal arrived with a delay. CONSTITUTION:In order to synthesize a new frequency, when the frequency division number of a variable frequency divider 2 is changed, the change in a phase comparator 8 is detected as a phase difference with a fixed frequency divider 7 and an error signal 9 is outputted. On the other hand, a control circuit 11 compares the arrival times every time the circuit receives two signals with lead and lag and outputs a reset signal 12 to the variable frequency divider 2 and the fixed frequency divider 7 at the arrival of the signal with a delay and the variable frequency divider 2 and the fixed frequency divider 7 are reset upon every receipt of the reset signal 12. Thus, the outputted frequency is changed by the control of the output signal of a low pass filter 10 and is the same frequency as the output of the fixed frequency divider 7, then the outputs are inputted simultaneously to the phase comparator 8, no error signal 9 is outputted and then the control is made complete. Thus, the oscillating frequency is quickly adjusted.
申请公布号 JP3077151(B2) 申请公布日期 2000.08.14
申请号 JP19900032861 申请日期 1990.02.13
申请人 发明人
分类号 H03L7/187;H03L7/18;H03L7/199 主分类号 H03L7/187
代理机构 代理人
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