发明名称
摘要 A novel FIFO buffer system has an error detection and correction device for effectively detecting and correcting errors therein. The system comprises M number of data storage blocks arranged in parallel for temporarily storing N-bit input digital data and generating storage state signals including full flag and empty flag signals representative of the full and the empty states thereof; an error detector, responsive to the storage state signals, for generating full error signals and empty error signals representative of the errors present among the full flag signals and empty flag signals; and an error corrector, responsive to the full error and the empty error signals, for generating full error correction signals and empty error correction signals for correcting the erroneous storage state occurred in the corresponding data storage means thereto.
申请公布号 JP3076205(B2) 申请公布日期 2000.08.14
申请号 JP19940294175 申请日期 1994.11.29
申请人 发明人
分类号 G11C7/00;G06F11/10;G11C29/00;H03M13/00;(IPC1-7):G11C7/00 主分类号 G11C7/00
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