发明名称
摘要 <p>PROBLEM TO BE SOLVED: To reduce the processing load of a CPU and to accelerate data transfer speed by passing through a processing request to an MPOA data processing part when a local bus controlling part receives the processing request, processing it when the MPOA data processing part can processing it and requesting the CPU to process it via a system bus controlling part when it can not process it. SOLUTION: In this ATM network data processing adding device 40, a system bus controlling part 41 is connected to a system bus 30 and a local bus controlling part 42 is connected to a local bus 50. The part 42 receives a processing request to a CPU and request an MPOA data processing part 44 for processing. When the part 44 notifies the part 41 of a CPU processing request, the part 41 sends the request to the system bus and gives a processed result from the CPU to the part 44 or the part 42. The part 42 sends the processed result to the bus 50.</p>
申请公布号 JP3075239(B2) 申请公布日期 2000.08.14
申请号 JP19970324712 申请日期 1997.11.26
申请人 发明人
分类号 H04Q3/00;H04L12/28;H04L12/70;H04L12/701;H04L12/763;H04L12/771;(IPC1-7):H04L12/28;H04L12/56 主分类号 H04Q3/00
代理机构 代理人
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