| 摘要 |
PROBLEM TO BE SOLVED: To generate an optional offset from an initial state vector and also to generate a state vector with little power consumption and little gate delays by permitting first logic circuits to generate plural-bit logical combinations and connecting the second logic circuit to receive the plural-bit logical combinations. SOLUTION: A matrix multiplication circuit 320 to be used in a matrix generating circuit includes the n logic circuits 370-374 and corresponds to the respective elements of the state vectors S11 to S1n. For example, the logic circuit 370 among the respective ones receives row elements m11 to m1n of a shift matrix and column elements S01 to S0n of an input state matrix. The matrix multiplying circuit includes the first logic circuits 380-383 and each of them calculates the logical product of corresponding row element and the column element in the shift matrix and the state matrix. The second logical circuit 390 generates the exclusive logical sum of the plural bit logical product signals of the respective state matrix elements S11. The circuit is very much advantageous, when a matrix multiplication with little gate propagation delay is calculated. |
