SEMICONDUCTOR DEVICE AND ITS FABRICATION

摘要

PROBLEM TO BE SOLVED: To reduce chip size by integrating a plurality of memory cells in a plurality of ROMs arranged in X direction as word lines and connecting the drain regions and source regions of a plurality of memory cells arranged in Y direction commonly with respective bit lines and source lines. SOLUTION: Source region 23 and drain region 24 on the major surface of a semiconductor substrate 1 is covered with an insulation film 7 of silicon oxide and laminated with a gate 28 of polycide film laminated with a polysilicon film and a high melting point metal silicide, e.g. tungsten silicide, through a gate insulation film 26 of silicon oxide film. The gate 28 is connected with the gate 28 of an FET in other block adjacent in X direction by specified number and it is a word line extending in X direction. A common source line is connected with a common source region 23 and a main bit line is connected with a common drain region 24 through a select FET provided at the other end of each element forming region.