NONVOLATILE SEMICONDUCTOR MEMORY

摘要

PROBLEM TO BE SOLVED: To obtain an NAND type EEPROM in which a plurality of erase blocks can be set in one NAND cell block. SOLUTION: The NAND cell block 1 of a memory cell array comprises NAND cells in which a plurality of memory cell transistors MC are connected in series between a bit line BL and a source line SL. Select transistors SST, GST are provided between the bit line BL and the source line SL of the NAND cell. A block isolate/select transistor ST is provided between two concatenate memory transistors MC15 and MC16 in the NAND cell and the NAND cell block 1 is divided into two memory cell units MU0, MU1. One of these memory cell units is selected as erase unit and flash erase of data in erase unit or data write in page unit is effected.