DELAYED SYNCHRONOUS LOOP AND METHOD

摘要

PROBLEM TO BE SOLVED: To increase the area for an operation frequency by shifting a delay clock signal only for a reference phase value and generating a preceding clock signal, when the phase difference of the delay clock signal to a reference clock signal is larger than the reference phase value and generating the preceding clock signal without phase shifts, when the phase difference is equal to or smaller than the reference phase value. SOLUTION: The initial states of output signals of NAND gates 49 and 51 are high. The initial state of a phase shift control signal INV is low, and the initial state of an output signal N50 of an inverter 55 is high. When a delay clock signal DCLK2 which generates a clock input signal for flip-flops 45 and 47 is activated to high, the logical state of a reference clock signal RCLK2 is low. Thus, although the output signal of the gate 49 maintains high state, the output signal of the gate 51 becomes low. Consequently, the signal INV continues to maintain a low state and the output signal N50 of the inverter 55 becomes low.