发明名称 CERAMIC MULTILAYER WIRING BOARD
摘要 PROBLEM TO BE SOLVED: To provide a ceramic multilayer wiring board which can work a semiconductor integrated circuit element of a high speed performance having an operating frequency exceeding, for example, 400 MHz, normally and stably by making the thickness of a metallized layer for a power supply large to reduce an electric resistance of it without generating stacking faults in upper and lower insulating layers which have the intervening metallized layer. SOLUTION: This ceramic multilayer wiring board is constituted of an insulating substrate 1 made by stacking a plurality of ceramic insulating layers 1a-1e and metallized wiring conductors 5 for a signal and metallized layers 3, 4 for a power supply, with the metallized conductors and the metallized layers disposed between the insulating layers 1a-1e. The metallized layers 3, 4 are 10 to 20μm in thickness and have many openings 3a, 4a having a size W2 of 50-240μm which are disposed at intervals of 100-300μm. In this substrate, an electric resistance of the metallized layers 3, 4 can be reduced without generating stacking faults in the insulating layers 1a-1c and thereby a semiconductor integrated circuit element 2 of a high speed performance can be operated normally and stably.
申请公布号 JP2000223614(A) 申请公布日期 2000.08.11
申请号 JP19990022104 申请日期 1999.01.29
申请人 KYOCERA CORP 发明人 TOKI HIROSHI
分类号 H05K1/02;H01L23/12;H05K3/46;(IPC1-7):H01L23/12 主分类号 H05K1/02
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