| 摘要 |
<p>The invention concerns a fast-chainable elementary adder receiving three bits A, B, C for supplying two complementary sum outputs (SO, SO*), and two complementary carry digit outputs (CO, CO*) comprising: a first stage with three differential pairs P1, P2, P3 each receiving a respective bit A, B, C and its complement A*, B*, C*, the three pairs having common output branches and being each powered by an identical current I, the output branches comprising each three resistors R1, R2, R3 and R4, R5, R6 connected in series to a reference potential (M), said resistors defining three intermediate nodes A1, A2, A3 in the first branch, B1, B2, B3 in the second branch the carry digit outputs being effected on the nodes A2 and B2; a second stage comprising three other differential pairs P4, P5, P6 whereof the inputs are connected to the nodes A1 and B3 for pair P4, A2 and B2 for pair P5 and A3 and B1 for pair P6, the pairs P4 and P6 having each a common branch with the pair P5 and a non-common branch, the sum outputs of the adder stage being each constituted by the combination, in accordance with an OR function, of the logic states appearing respectively on the non-common branch of one of the pairs P4 and P6 and on the common branch of the other. The invention is applicable to fast adders, in particular, in algorithms processing rapid signals in real time, pulse response filters.</p> |
