发明名称 |
Multilevel metal wiring used in semiconductor chip production is improved in quality by carrying out an integrated annealing or tempering step at the start of inter-level dielectric deposition |
摘要 |
Method for improving multilevel metal wiring quality involves carrying out an integrated annealing or tempering step at the start of inter-level dielectric deposition. Preferred Features: The wafer may be preheated to the annealing temperature in a first stage of inter-level dielectric deposition or inter-level dielectric deposition is carried out after annealing and cooling the wafer.
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申请公布号 |
DE19903195(A1) |
申请公布日期 |
2000.08.10 |
申请号 |
DE19991003195 |
申请日期 |
1999.01.27 |
申请人 |
SIEMENS AG |
发明人 |
LEHR, MATTHIAS |
分类号 |
H01L21/768;(IPC1-7):H01L21/768;H01L21/316;H01L21/324 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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