METHOD OF MAKING A HIGH-VOLTAGE TRANSISTOR WITH MULTIPLE LATERAL CONDUCTION LAYERS

摘要

A method for making a high voltage insulated gate field-effect transistor having an insulated gate field-effect device structure with a source and a drain comprises the steps of forming the drain (19) with an extended well region (17) having one or more buried layers (18) of opposite conduction type sandwiched therein. The one or more buried layers (18) create an associated plurality of parallel JFET conduction channels (25) in the extended portion of the well region. A minimal number of processing steps are required to form the parallel JFET conduction channels which provide the HVFET with a low on-state resistance.